Startsteuerung

摘要

1,202,674. Data processing; gated counters. INTERNATIONAL BUSINESS MACHINES CORP. 19 March, 1969 [1 April, 1968], No. 14319/69. Heading G4A. A data processing unit comprises a plurality of buffers in the input to arithmetic circuitry for receiving operand data strings, and means to feed the operand(s) in the highest-priority completed string from its buffer to the arithmetic circuitry. A two-stage floating-point adder receives a pair of operands from any of 3 buffers (pairs of registers) when a START signal respective to the buffer is produced. When a buffer is to be loaded, a respective SELect signal is produced to set a coded representation of the buffer identity into the lowest empty position (pair of bi-stables) of a stack as indicated by a counter, the SELect signal then incrementing the counter. When a buffer is completely loaded (which may take a plurality of memory accesses), it produces a respective Unit Full signal. A priority network determines the buffer identity furthest down the stack for which the Unit Full signal is present, and provided the adder is not full, a START bi-stable respective to this buffer is set to produce its START signal and reset the stack position containing the buffer identity. Buffer identities automatically move down the stack to fill up empty positions, via auxiliary pairs of bi-stables. After a buffer has been freed, a respective ACcePT signal decrements the counter and resets the respective START bi-stable. Production of SELect signals is inhibited when the counter indicates the stack is full. Counter (Fig. 7).-An input at any of SEL 1-3 produces a signal INC and an input at any of ACPT 1-3 produces a signal DEC, except that if both would thus be produced simultaneously, neither is produced. A signal I/D is produced if either INC or DEC is. INC and DEC respectively increment and decrement the binary counter which has two counting bistables PH11Cl, PH11C2, the count in which is periodically (by clock pulses t 6 ) copied into auxiliary bi-stables PHC11, PHC22 which, together with signals INC, DEC, I/D, control input gates 101-107 of the counting bi-stables PH11C1, PH11C2, the latter being enabled to respond to the gates by coincidence of I/D with clock pulses t 11 at AND 108.