发明名称 VERTICAL DEFLECTING CIRCUIT
摘要 PURPOSE:To decrease charge and discharge currents and also to reduce the numbers of pins for a discharging resistance to be equipped in IC by making a vertical blanking interval shorter than vertical oscillation pulses. CONSTITUTION:An output pulse through inverter 21 and an oscillation pulse of oscillation circuit 11 wider than that are applied to AND circuit 22, which generates two pulses. Namely, one pulse is made to rise lagging the oscillation pulse, and the other is more expanded in width than the oscillation pulse. In this way, these output pulses are supplied to FF circuit 23, where they are inverted and supplied to saw tooth wave oscillator 12. As a result, discharge and charge currents can be reduced easily and accurately and in case of IC-implementation, also the number of pins can be reduced while a discharge resistance can be installed in IC.
申请公布号 JPS5549072(A) 申请公布日期 1980.04.08
申请号 JP19780123027 申请日期 1978.10.05
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 KATAFUCHI HISASHI
分类号 H04N3/16 主分类号 H04N3/16
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