| 摘要 |
PURPOSE:To simplify double-length process and data interchange process between registers, by providing two data buses, a logical operation unit, input inhibition circuit, an two data latches, and a bus driver. CONSTITUTION:Either internal data bus UB29 or LB30 is led to either input of logical operation unit ALU20, and the other is to the other input of ALU20. Data latch ALT25 connected to the output of ALU and data latch BLT26 sharing an input with circuit 24 are both provided and data of latches 25 and 26 are transferred to buses 29 and 30 via bus driver 27. As a result, although the logical operation bit length of ALU20 is four-bit length, data of respective registers 6, 8, 9, 13, and 14, ROM5, and RAM11 are transferred to buses to 29 and 30, further transferred to buses 29 and 30 again through latches 25 and 26, and then fetched by other resistors or RAM, so that double-length data transfer of 4-bit length can be attained in one instruction execution cycle. |
