| 摘要 |
PURPOSE:To compare the parity bit of the respective registers of plural number with only the parity bit on the data bus in the next cycle, thereby to facilitate to detect the mistake in setting of the respective registers. CONSTITUTION:The data 1 located on the data bus which is given from exterior and the data parity 2 are given to the registers 3, 4 and the registers 5, 6. When the respective registers 3 to 6 are selected in accordance with the designation of the register select signals 8 to 11 and when the clock 12 is applied to the register, the data 1 and the parity 2 are set. To the register 13, the select signals 8 to 11 and the clock 12 to set the parity 2 and the select signals 8 to 11. To the parity select circuit 19, the data parity outputs 15 to 18 are added, which are selected correspondingly to the select signals 8 to 11 memorized in the register 13. When either one of the registers 3 to 6 is selected, the output 20 of the circuit 19 is intended to the coincided with the output 21 of FF 7. The coincidence is checked by the comparator 22 to make easy the detection of the mistake in setting of the respective registers 3 to 6. |
