发明名称 Sampled error phaselock or frequencylock systems
摘要 Phaselock or frequencylock systems employ sampling means and memory means to effect control. Adjustments in phase or frequency are made according to stored signals and the stored signals are updated in accordance with samples of an error indicative signal.
申请公布号 US4190807(A) 申请公布日期 1980.02.26
申请号 US19780921676 申请日期 1978.07.03
申请人 ROCKWELL INTERNATIONAL CORP 发明人 WEBER, ROBERT J
分类号 H03C1/04;H03L7/081;(IPC1-7):H03B3/04 主分类号 H03C1/04
代理机构 代理人
主权项
地址