| 摘要 |
PURPOSE:To insure the normal operation when the program is executed with only the order function featuring the lower-rank function by providing the selection circuit to select the orders according to each function in addition to part of each function in case each function of the microcomputer or the multiple chip is formed. CONSTITUTION:Instruction decoder ID includes decoder blocks DA, DB, DC and DD each, and test terminal T to test the ever-chip plus signal line IP to be used as the signal line which supplies input to the prescribed register, buffer and others within the ever-chip through input boats IA, IB and IC each. Then input terminals of AND gates GA, GB and GC are connected to those input boats; and terminal T is connected to the other terminal respectively. Furthermore, the output of gate GA is connected to FF FA, the output of gates GB and GC are connected to FF FB and FC via OR gates OB and OC, and system reset signal R is connected to FF FA- FC each. |
