| 摘要 |
The circuit includes a gate (11) for transmitting starting signal when an OR gate (12) receives PEREN and first clock (T1), for inputting data in data bus and for cutting data bus at no EREN singal, a gate for transmitting latched data at every first clock, a priority encoding test logic circuit (18) for transmitting a certain logic state during one period of the first clock which appears first time from MSB or MLB of latched data, a gate (20) for transmitting tested signal as a bit clear signal by second clock which is delayed less than one period of first clock, and a gate (23) for generating priority encoding quitting signal when data corresponding to a certain logic in number are transmitted.
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