| 摘要 |
A digital switch for switching word formatted PCM digital data is disclosed. The data of each PCM word is serially bit switched rather than being switched in parallel as in conventional PCM switches. This is achieved by time multiplexing corresponding word bits of respective incoming channels or inlets onto a single data highway to form a bit interleaved digital bit stream. Data on the highway is switched through a RAM under control of a control memory according to the required connections so as to rearrange the order of the data bits. The rearranged data is demultiplexed to the respective outgoing channels or outlets. To avoid less of alignment of word boundaries at the outlets, as between respective channels, the switch determines those connections which incur a switch cycle delay relative to those which do not. This is done by comparing the read and write address controlling the switch memory and when the write address is equal to or greater than the read address the particular bit being switched is delayed on the highway by one cycle. In the converse situation the delay has already occurred in the RAM and no further delay is introduced. The delay is caused by a delay equalizer circuit including a further RAM which receives all data on the highway and introduces a one cycle delay thereto. A by-pass connection enables data on the highway to by-pass the further RAM and hence avoid the delay. An AND/OR select gate selects data from the further RAM or the by-pass connection as the case may be. Thus all data through the switch incurs an equal delay. A synchronization signal at the switch input, for word aligning the data, is delayed by one cycle at the switch outlet. A method for switching data is also claimed. |
