| 摘要 |
PURPOSE:To make it possible to detect completely even an I/O register storage error consisting of even bits by comparing data, which is stored in an I/O register and is outputted, with data, which is inputted to the I/O register, in a comparison circuit. CONSTITUTION:Comparison circuits 301...303 are provided in the output side of I/O registers 201...203 respectively. Now, assuming that R1 I/O register 201 is assigned by the code signal sent through FUN line, this code signal makes AND gate 6 enable through receiver 4 and decoder 5. Next, when the sampling pulse from DTS line is inputted to receiver 3, transfer data is stored in register R1 through gate 6. At the same time, data which is stored in register R1 and is outputted is compared with data of the input side in comparison circuit 301, and the storage error of input information in register 201 is detected. As a result, even an I/O register storage error consisting of even bits can be detected completely. |
