发明名称 INSPECTION METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PURPOSE:To increase the processing ability, by measuring a plurality of IC's parallelly with one set of tester, discriminating them respectively and measuring the total with the measuring time for one piece's share. CONSTITUTION:The test pattern 8 is generated 1, and it is parallelly fed to the measured IC's 2, 3 and the outputs 9, 10 are respectively given to the comparison circuits 4 and 5. The expectation pattern 11 is given to the circuits 4 and 5 from the pattern generating section 1, comparison is made with the timing of the strobe signal 14, and the information 12, 13 resulted from the comparison of each pattern are memorized in the registers 6, 7. When the content of the registers 6 and 7 is inspected after the end of test pattern, the propriety of IC's of a plurality can be judged. Thus, a plurality of IC's can be inspected with the inspection time for one piece and the processing ability can be increased.
申请公布号 JPS5476074(A) 申请公布日期 1979.06.18
申请号 JP19770144126 申请日期 1977.11.30
申请人 NIPPON ELECTRIC CO 发明人 NIGORIKAWA ATSUSHI
分类号 G01R31/28;G01R31/26;G06F11/00;G06F11/22 主分类号 G01R31/28
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