Storage device

摘要

The proposed storage device comprises a memory unit for storing control information connected to a constant register, to which there is connected a functional return address jump register, a next address register, an address digit modification attribute register, and an analysis code register, to which there is connected an analysis signal forming decoder. To the outputs of the analysis signal forming decoder there are connected main coincidence circuits which form a matrix having columns in a number equal to that of the address digits of the memory unit for storing control information being modified, and lines in a number determined by the digit capacity of the analysis code register. The proposed storage device further includes additional coincidence circuits whose number is equal to that of the address digits of the memory unit for storing control information being modified, each of said additional coincidence circuits being connected to the main coincidence circuits and the address digit modification attribute register; priority commutators for commutating modifiable address digits of the memory unit for storing control information, and priority commutators for commutating non-modifiable address digits of the memory unit for storing control information the number of the respective priority commutators is equal to that of the modifiable and non-modifiable address digits, respectively, of the memory unit for storing control information. Each of the commutators is connected to an instruction unit, a coder, the memory unit for storing control information, the functional return address jump register, and the next address register.