| 摘要 |
In a data processing system having a plurality of units coupled to the transfer of information therebetween over a common electrical bus or for transferring information via a communication channel to other data processing systems during asynchronously generated information bus transfer cycles, an apparatus exists for reformatting data for transfer over the common electrical bus or via the communication channel. The apparatus is comprised of an eight-way multiplexer responsive to control bits for selecting one of eight different fpr,ats during write or read operations to or from a memory. Additionally, during read operations, the apparatus transfers a return address from a unit requesting information to the address bus so that data read from memory may be transferred to the requesting device. The formatting control bit is similarly reformatted from the data bus to the address bus bit. |
