| 摘要 |
PURPOSE:To expand the delay setting range of timing pulses up to two cycles by putting two delay counters in two-cycle operation alternately. CONSTITUTION:The timing signal generator is provided with a cycle counter 2 which counts a variable reference clock 101 and generates a cycle pulse 102 from a counting end output and the two delay counters 5a and 5b independently. Then a multiplexer 3 puts the two delay counters 5a and 5b in the two-cycle operation alternately. Namely, the two delay counters 5a and 5b can count up to two cycles in a one-cycle shift state. Consequently, the delay time setting range of the timing pulses is expanded up to two cycles. |
