发明名称 ROUNDDOFF SYSTEM FOR FLOATING DECIMAL POINT COMPUTATION
摘要 PURPOSE:To enhance computation accuracy without lowering the speed of floating decimal point computation by incorporating the digit overflow detection circuit to the circuit which performs round-off and by branching the digit overflow into overflow processing sequence.
申请公布号 JPS52112249(A) 申请公布日期 1977.09.20
申请号 JP19760028106 申请日期 1976.03.17
申请人 HITACHI LTD 发明人 YANAGIDA TOMOATSU
分类号 G06F7/38;G06F7/00;G06F7/483;G06F7/76 主分类号 G06F7/38
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