| 摘要 |
PURPOSE:To suppress jitter due to mis-control of a reference carrier signal by providing a memory outputting a predetermined control data representing a phase lag and phase lead region in response to an input of a main data signal. CONSTITUTION:Main data signals X1-X4 and Y1-Y4 are inputted to a memory 14 as address data A1-A8. The memory 14 outputs the content of a relevant address written in a ROM as control data D0, D1. The control data D0, D1 are added by an adder 13 and fed to a voltage controlled oscillator 9 as an analog phase control signal 25. The relation between the control data D0, D1 and the address data A1-A8 is so decided that when the signal point position represented by the address data A1-A8 is in a phase lag area, both the control data D0, D1 are logical 0, and when it is in a phase lead region, both the control data D0, D1 are logical 1 and when it is in the phase coincidence region, either of the control data D0, D1 is logical 1 and the other is logical 0. |
