| 摘要 |
<p>According to the present invention, methods and apparatus for reducing memory access latency are disclosed. When a new entry is made to translation look aside buffer (110), the new TLB entry points to a corresponding TLB page of memory (108). Concurrently with the updating of the TLB, the TLB page is moved temporarily closer to a processor (102) by storing the TLB page in a TLB page cache (114). The TLB page cache (114) is temporarily closer to the processor than is a main memory (108).</p> |
