发明名称 DUMMY FAULT SYSTEM
摘要 PURPOSE:To generate the dummy fault of random contents by adding a simple circuit by moving a scan path by OR of a scan instructing signal and a dummy fault instructing signal and generating a dummy fault. CONSTITUTION:In an information processor which includes plural pieces of LSIs 20, 21 provided with a scan path and an error detecting circuit, and can operate the scan path independently by an LSI unit, the operation of the scan path of the LSIs 20, 21 is executed by OR of scan instructing signals 101, 102 for instructing the operation of the scan path to the LSIs 20, 21, and dummy fault instructing signals 104, 105 for instructing the generation of a dummy fault to the LSIs 20, 21. In such a manner, not only and error is generated by a dummy fault, but also a phenomenon being similar to an actual fault such as a data breakdown and the propagation of an error, etc., is generated, and the fault resisting function can be confirmed.
申请公布号 JPH03255542(A) 申请公布日期 1991.11.14
申请号 JP19900054049 申请日期 1990.03.05
申请人 NEC CORP 发明人 SATO YOICHI
分类号 G06F11/22 主分类号 G06F11/22
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