| 摘要 |
PURPOSE:To perform time-division transfer between an external and an internal memory by storing an interface circuit with conditions of reading from and writing to the external memory, and switching a read and a write mode on every one-byte tansfer. CONSTITUTION:A CPU1 and a channel device 2 are provided, and an I/O interface circuit 4 for plural channels performs data transmission and reception between an RAM42 and an external memory RAM32. In addition to an MPU41, a DMA controller 43, and an input-output buffer circuit 44, the circuit 4 is provided with a DMA controlling circuit 45 having a mode setting circuit, a channel deciding circuit, a channel address circuit, etc., and is stored wirh a write state for reading data out of the RAM42 to the RAM32, and a read state for reverse operation; and a write and a read mode are switched on every one-byte transfer. For example, one-byte data is written in the RAM32 and then one-byte data is read out of the RAM32 on the basis of the storage state of the read state and then transferred to the RAM42, thus performing time-division transmission and reception. |
