| 摘要 |
PURPOSE:To obtain the properly rounded normalization result for any input data by preliminarily detecting the condition of mantissa data the result of which becomes non normalization number by the rounding normalization processing and shifting more one bit in the shift processing for normalization. CONSTITUTION:The normalization circuit normalizing the negative floating point number of the expression of the complement 2 is provided with a consecutive zero detection circuit 3 detecting the number of bits from the highest order bit of the input mantissa data for normalization to the initial '0', a consecutive 1 detection circuit 4 discriminating how many bit is continued after the bit lower by one bit from the initial '0', and a shift amount correction addition circuit 5 adding '1' to the output of the consecutive zero detection circuit 3 in the case the decision result of this consecutive 1 detection circuit 4 continues for more than the effective digit number of mantissa data at the time of normalization processing. |
