INFORMATION PROCESSING UNIT

摘要

PURPOSE:To attain an analysis with high accuracy in applying debug or retrieval of a fault by designing the titled unit that the timewise relation when data read from a main storage device exists on a data bus and the timing when the data is stored in a register of a processor are equal to that at normal running when a SS read instruction is executed in the step mode. CONSTITUTION:In a system that a main storage device 6 and plural processors are constituted to use an information transfer bus 8 in common, and when a processor executes an instruction to read the content of the main storage device in the step mode, the information read from the main storage device is stored in the own register of a processor other than the processor executing the instruction reading the content of the main storage device and the said processor keeps transmission of the content of the register to the information transmission bus 8 except the time when the information transfer bus is used for other purposes. Thus, a large quantity of hardware exclusive for the step mode is not required to be provided to the main processor.