发明名称 UN DISPOSITIVO DE MEMORIA ELECTRONICA DE SEGURIDAD
摘要 <p>1,105,624. Gating circuits. COMPAGNIE DES FREINS ET SIGNAUX WESTING- HOUSE. 5 April, 1965 [3 April, 1964], No. 14434/65. Heading H3T. A fail-safe switching circuit comprises a transistor having a repetitive signal as input, and a feedback path from output to input comprising a rectifier, resistor and capacitor to integrate the feedback signal and hold the transistor conducting as long as the repetitive signal appears at the output. In Fig. 1, transistor 1 acts as an AND gate with three inputs. In the absence of an input to transistor 25, the transistor 1 is either cut off or saturated according to the state of switch 9 (in practice a source of trigger pulses). Oscillations applied to transistor 25 are rectified by diode-capacitor circuit 20, 21 and, if switch 9 is open, will bias the base of transistor 1 to an intermediate state of conduction when the oscillations will appear on the collector output line. The integrating feedback circuit will maintain this state and the oscillations will pass, gated by the switch 9. Any component failure will suppress the oscillations at the output. In a modification (Fig. 3, not shown) a further transistor (49) is inserted in the feedback path to act as an OR gate as in Specification 1,095,071, with the trigger input applied via another transistor (63) to the base of the further transistor (49). In another version (Fig. 4, not shown) the further transistor (70) acts as an AND gate in the feedback path (see Specification 1,099,001), receiving the oscillations and the integrated feedback voltage, the trigger pulses being applied directly to the output transistor as in Fig. 1.</p>
申请公布号 ES311350(A1) 申请公布日期 1965.06.01
申请号 ES19500003113 申请日期 1965.04.02
申请人 COMPAGNIE DES FREINS ET SIGNAUX WESTINGHOUSE 发明人
分类号 G11C11/40;G11C14/00;H03K3/037;H03K19/003;H03K19/007;(IPC1-7):G11C11/40 主分类号 G11C11/40
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