| 摘要 |
PURPOSE: To disable decoded chip forbidden mode by controlling a quadrature channel decoded chip using a state logic circuit implemented in a programmable logic unit and generating a digital angle when the state logic circuit is updated at every data sampling time. CONSTITUTION: An HCTL-2000 chip 30 included in the interface for a shaft angle encoder has pins 6, 7 for receiving lead/lag angular phase channel signals from the shaft angle encoder. A CLK input for the HCTL-2000 is applied to a pin 2 from the clock signal source of a radar through a terminal 31 while SEL and -OE signals are received at pins 3, 4. These control signal are generated from a state logic circuit section 32. An EP 310 at the circuit section 32 applies a reset pulse -RST to a pin 5 for the HCTL-2000 and the chip outputs D0-D7 therefrom are applied to a 8 bit parallel bus 33. A quadrature square wave is then changed to a digital angle.
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