发明名称 CLOCK PHASE ADJUSTMENT CIRCUIT AND COMMUNICATION EQUIPMENT USING THE CIRCUIT
摘要 PURPOSE:To realize the adjustment of the phase of a clock signal with a small scale circuit and low power consumption. CONSTITUTION:A differentiation circuit 2 detects a rising/falling timing of a clock signal recovered by a clock recovery section 1, a phase counter 3 is initialized by the rising or falling timing of the clock signal to count a phase shift. A count decoder 4 generates a timing pulse deciding the phase based on the count output and the phase shift information, a latch circuit 5 latches the clock outputted from the clock recovery section 1 in the timing of the pulse and the decoder 6 decides the phase of the clock based on phase shift information and outputs the clock signal whose phase is adjusted.
申请公布号 JPH0856152(A) 申请公布日期 1996.02.27
申请号 JP19940189402 申请日期 1994.08.11
申请人 HITACHI LTD 发明人 SHIMODA SHINICHI;SUDO SHIGEYUKI;TAKAHARA YASUAKI;SUZUKI AKIHIRO
分类号 H03L7/00;H04L7/02 主分类号 H03L7/00
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