Bit-line sense amplifier capable of compensating mismatch between transistors, and semiconductor memory device including the same

摘要

A bit-line sense amplifier may include a pull-up driving circuit, a pull-down driving circuit and a latch-type sense amplifier. The pull-up driving circuit including a plurality of PMOS transistors connected between a power supply voltage line and a first driving power supply line, and may be configured to provide a first driving current on the first driving power supply line in response to an up control signal. The pull-down driving circuit may be configured to provide a second driving current on a second driving power supply line in response to a down control signal. The latch-type sense amplifier may be connected between the first driving power supply line and the second driving power supply line, and may be configured to sense and amplify a voltage difference between a bit line and a complementary bit line.

主权项

1. A bit-line sense amplifier, comprising:
a pull-up driving circuit connected between a power supply voltage line and a first driving power supply line, and configured to provide a first driving current on the first driving power supply line in response to an up control signal; a pull-down driving circuit configured to provide a second driving current on a second driving power supply line in response to a down control signal; and a latch-type sense amplifier connected between the first driving power supply line and the second driving power supply line, and configured to sense and amplify a voltage difference between a bit line and a complementary bit line, wherein the pull-down driving circuit comprises: a voltage adjusting circuit configured to regulate a power supply voltage on the power supply voltage line in response to a reference voltage to provide a first voltage on a first node; a first driving circuit configured to generate a gate driving signal based on the down control signal and the first voltage; and a second driving circuit configured to provide the second driving current on the second driving power supply line in response to the gate driving signal, and wherein the voltage adjusting circuit comprises: a differential amplifier having an inverted input terminal to which the reference voltage is applied, and a non-inverted input terminal connected to the first node; and a PMOS transistor having a gate connected to an output terminal of the differential amplifier, a source connected to the power supply voltage line, and a drain connected to the first node.