| 摘要 |
A channel module (34) has an interchangeable port intelligence system (71a, 71b, 71c) at a front end which is connected to a memory interface system (72) at a back end. Each port intelligence system (71a, 71b, 71c) provides one or more ports (33) for connection to fiber optic channels (32) and, the various port intelligence systems (71a, 71b, 71c) are distinguishable by a particular bit rate in which each supports. Data from the port intelligence system (71a, 71b, 71c) is bit sliced and forwarded to the memory interface system (72). In the system (72), the data is stored in receive memory (84) in a distributed manner over a plurality of receive memory components (131). The bit slicing simplifies the input/output interface to the receive memory (84) and enables storage of data with a common format, regardless of the rate at which the data was received from the channel (32). When data is read from the receive memory (84), each of the receive memory components (131) contributes bits in order to reconstruct the data.
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