发明名称 |
Method of forming a controlled low collector breakdown voltage transistor for ESD protection circuits |
摘要 |
An npn transistor having a low collector-base breakdown voltage. An emitter region (104, 106) of a first conductivity type is located in a semiconductor substrate (102). A base region (14) of a second conductivity type is located within the emitter region (104,106) and a shallow collector region (18) of the first conductivity type is located within the base region (14). The shallow collector region (18) may be doped with arsenic and/or phosphorus such that the dopant concentration and depth of the shallow collector region (18) provide a low collector-base breakdown voltage.
|
申请公布号 |
US5607867(A) |
申请公布日期 |
1997.03.04 |
申请号 |
US19950475268 |
申请日期 |
1995.06.07 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
AMERASEKERA, AJITH;CHATTERJEE, AMITAVA |
分类号 |
H01L27/02;(IPC1-7):H01L21/265 |
主分类号 |
H01L27/02 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|