发明名称 LAMINATED CHIP INDUCTOR
摘要 PROBLEM TO BE SOLVED: To provide a laminated chip inductor which can easily correspond with downsizing and has a structure suited to narrow tolerance, and by which a lead conductor can be easily formed even in the case of downsizing and the number of steps be reduced for low-cost manufacturing. SOLUTION: A conductor pattern that an electric insulation layer and a conductor pattern are alternately laminated is connected sequentially to form a stacked coil 24 inside an electric insulator 22 in the lamination direction, and both ends of the coil 24 are connected with an external electrode 28 on the outer surface of a laminated chip by means of a lead conductor 26. In such a laminated chip inductor 20, a pair of external electrodes are printed on one outer surface of the laminated chip vertical to the direction of coil axis, and both lead conductors are laminated while they are buried in the side surfaces of the laminated chip parallel in the direction of coil axis and the surface of the conductor is exposed.
申请公布号 JP2002260925(A) 申请公布日期 2002.09.13
申请号 JP20010056565 申请日期 2001.03.01
申请人 FDK CORP 发明人 SUZUKI YASUO;OBA YOSHINARI
分类号 H01F41/04;H01F17/00;(IPC1-7):H01F17/00 主分类号 H01F41/04
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