| 摘要 |
An N-input transistor logic circuit includes two or four series-connected transistor arrays connected between two power lines. The gates of the transistors are connected to the N inputs to account for varying parasitic input capacitances, and equalizes the resulting time delays between the N-inputs and the logical unit output. Specifically, in each of the arrays each of the transistors is connected to one of the N inputs, and is separated from a first power line by X other transistors in the respective array. For each of the input terminals, the sum of X for all the arrays is a constant, namely, 2N-2 for four arrays and N-1 for two arrays.
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