TIMING RECOVERY SYSTEM FOR A DIGITAL SIGNAL PROCESSOR

摘要

A timing recovery network for a digital signal processor is provided to provide an interpolator, a control circuit network, and the controlled delay network, thereby using the timing recovery system as a digital signal receiver such as a television signal receiver. A timing recovery network for a digital signal processor comprises the followings: a source of samples indicating received signals; an interpolator(12) for generating samples taken in synchronized time in continuous symbols from a transmitter in response to a control signal indicating pre-selected delay signals from a controlled delay network; a control circuit network for providing the control signal; and the controlled delay network which is responded by a delay offset signal and an output signal from the interpolator.