| 摘要 |
PROBLEM TO BE SOLVED: To provide an information processor and an interface circuit for effectively reducing latency when a bus mater performs access to a peripheral module such as a register. SOLUTION: This information processor is provided with a bus master (1100) operating synchronously with a first clock signal; a peripheral module (1200) operating synchronously with a second clock signal; and a dual port RAM (1210) as a storage means having a first access port for transferring data with a bus master synchronously with the first clock signal and a second access port for transferring data with the peripheral module synchronously with the second clock signal, wherein data transfer between the bus master (1100) and the peripheral module (1200) is executed via the dual port RAM. COPYRIGHT: (C)2008,JPO&INPIT
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