发明名称 Semiconductor device and method of manufacturing the same
摘要 A semiconductor device including an active cell region formed over the surface of a silicon substrate and including a vertical MOSFET, a drain electrode formed over the surface of the silicon substrate and leading out the drain of the vertical MOSFET from the back surface of the silicon substrate, an external drain terminal formed over the drain electrode, and a source electrode formed over the active cell region so as to be opposed to the drain electrode at least along three sides at the periphery of the external drain terminal over the active cell region and connected to the source of the vertical MOSFET.
申请公布号 US9431491(B2) 申请公布日期 2016.08.30
申请号 US201414282863 申请日期 2014.05.20
申请人 Renesas Electronics Corporation 发明人 Aoki Takashi;Korenari Takahiro
分类号 H01L29/76;H01L29/94;H01L31/062;H01L31/113;H01L31/119;H01L29/417;H01L29/66;H01L29/78;H01L23/482;H01L29/423;H01L29/06;H01L29/10 主分类号 H01L29/76
代理机构 McGinn IP Law Group, PLLC 代理人 McGinn IP Law Group, PLLC
主权项 1. A semiconductor device comprising: an active cell region formed over a surface of a semiconductor substrate and including a vertical transistor; an external gate terminal formed over the surface of the semiconductor substrate and electrical connected to a gate of the vertical transistor; a drain electrode formed over the surface of the semiconductor substrate and leading out a drain of the vertical transistor from a back surface of the semiconductor substrate; a plurality of external drain terminals formed over the drain electrode and electrically connected to the drain electrode; a source electrode formed over the active cell region so as to be opposed to the drain electrode at least along three side at a periphery of the external drain terminal and connected to a source of the vertical transistor; and a plurality of external source terminals formed over the source electrode and electrically connected to the source electrode,wherein the external drain terminals, the external source terminals and the external gate terminal are disposed at least in a pad layout of two rows×three columns.
地址 Kawasaki-shi, Kanagawa JP