Condition code system for universal data processors - with operation independent of instruction list list and mask to control selector to which condition bits are applied

摘要

The condition code unit for a universal data processor consists of a store (M1) containing masks and base addresses, addressed by the operating code of the machine instruction list (OPC). The mask controls a selector (SHN) to which the condition bits are applied and stored. Only bits selected by the mask appear in correctly assembled order at the output of the selector to form an 8-bit distance address (DADR). The distance address is combined with the base address (BADR) in an OR-gate constructed as a parallel adder, to form a second physical address (ADR2) for a second store (M2). The second store contains a table of all condition code values for the actual instruction list. Both stores can be replaceable non-volatile types if changes to the instruction list are infrequent; otherwise they are of the random access type.