REDUNDANCY DECODER IN SEMICONDUCTOR MEMORY DEVICE

摘要

PURPOSE: A redundancy decoder in a semiconductor memory device is provided to generate a correct decoding signal without affection of an output signal of an address buffer in response to a signal input through an option pad when changing the number of input/output data. CONSTITUTION: A redundancy decoder in a semiconductor memory device includes the first and second control signal generators, a plurality of address input portions(20-1,20-n), an option pad and a switching portion(40). The first control signal generator generates the first control signal enabled when an enable fuse is cut off. The address input portions outputs the first level signal in response to an address corresponding to a defect memory cell and outputs the second level signal in response to another addresses except the address. The second control signal generator(30) generates the second control signal for making a redundancy line replaced with a defect memory cell accessed only when the first level signal is output. The option pad generates the third control signal whose level is varied according to the number of the input/output data. The switch portion operates according to the number of the input/output data.