发明名称 PLL circuit
摘要 A PLL circuit includes a PLLic formed into an integrated circuit; a loop filter for receiving an output signal from the PLLic; a voltage-controlled oscillator having an oscillation frequency which is controlled according to an output signal of the loop filter for applying a controlled oscillation output signal to the PLLic, the voltage-controlled oscillator including a resonator and a negative resistor circuit; wherein a buffer amplifier functioning as a part of the voltage-controlled oscillator is incorporated into the PLLic, and the resonator and the negative resistor circuit of the voltage-controlled oscillator are disposed outside of the PLLic.
申请公布号 US5581584(A) 申请公布日期 1996.12.03
申请号 US19940277951 申请日期 1994.07.20
申请人 MURATA MANUFACTURING CO., LTD. 发明人 INOUE, ATSUSHI;HATA, TOSHIO;TAMAKOSHI, OSAMU;KOMAKI, TAKAYASU
分类号 H03L7/06;H03B1/00;H03B7/02;H03B7/06;H03L7/099;(IPC1-7):H03D3/24 主分类号 H03L7/06
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