| 摘要 |
For processing ATM cells in bidirectional, upstream and downstream data streams in an ATM module, whereby the processing speed is higher than the average cell rate and empty cycles without ATM cells occur in the cell stream, a processing logic of the module-for the purpose of an alternating processing of upstream or downstream cells-makes requests upstream and downstream for empty cycles to an empty cycle controller in order to receive processing time. The cells of the downstream data stream can be separately backed up and released in a buffer and, in this way, downstream empty cycles can be generated. Given a downstream empty cycle request, this request is allowed with priority over a simultaneous downstream request when an empty cycle occurs, and, given a downstream empty cycle request, an empty cycle is released delayed by one cycle length if an upstream request is simultaneously present but is otherwise immediately released.
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