发明名称 |
Address pattern generator |
摘要 |
An address pattern generator for generating regular addresses in a freely set aside area of the memory cell to be tested. The arrangement of the column address generator is structured the same as that of the row address generator wherein both the column address generator and the row address generator receive an add signal from a control circuit, address values from first and second maximum value registers and address values from first and second initial value registers. The column address generator has a comparator which compares an address to be supplied to the memory to be tested with the address value output from the first maximum value register and a selection circuit which selects address to be supplied to the memory using a signal output from the comparator.
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申请公布号 |
US5473616(A) |
申请公布日期 |
1995.12.05 |
申请号 |
US19930026999 |
申请日期 |
1993.03.05 |
申请人 |
ANDO ELECTRIC CO., LTD. |
发明人 |
TSUTSUI, YASUMITSU;TAKESHITA, HIROKI |
分类号 |
G01R31/3183;G01R31/3181;G11C29/10;G11C29/18;(IPC1-7):G06F11/00 |
主分类号 |
G01R31/3183 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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