发明名称 Vertical line multiplication method for high-resolution camera and circuit therefor
摘要 A vertical line multiplication method and circuit multiplies the number of vertical lines of a video signal which is imaged by use of 4 CCDs to transform the signal into another video signal having a higher resolution by controlling writing and reading of signals to and from a memory. A first memory (110) receives G1 channel data of 0.5H period from a G1 CCD and outputs the written data at twice a speed of a writing speed. A second memory (120) receives G2 channel data of 1H period from a G2 CCD and outputs the written data at twice the speed of the writing speed. A selection device (130) selects the data from the first and second memories alternatively and outputs selected signals sequentially as a wide bandwidth G signal. <IMAGE>
申请公布号 EP0792067(A3) 申请公布日期 1999.02.03
申请号 EP19970300894 申请日期 1997.02.12
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 LEE, HYO-SEUNG
分类号 H04N7/015;H04N7/01;H04N9/04;H04N9/09 主分类号 H04N7/015
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