Semiconductor device having a chip mounting portion on which a separated plated layer is disposed

摘要

The reliability of a semiconductor device is improved. A package of a semiconductor device internally includes a first semiconductor chip and a second semiconductor chip in which power MOS•FETs are formed and a third semiconductor chip in which a control circuit controlling the first and second semiconductor chips is formed. The first to third semiconductor chips are mounted on die pads respectively. Source electrode bonding pads of the first semiconductor chip on a high side are electrically connected with a first die pad of the die pads via a metal plate. On a top surface of the die pad 7D2, a plated layer formed in a region where the second semiconductor chip is mounted, and another plated layer formed in a region where the metal plate is joined are provided and the plated layers are separated each other with a region where no plated layer is formed in between.

主权项

1. A semiconductor device comprising:
a chip mounting portion including a first main surface, a first plated layer formed on the first main surface, and a second plated layer formed on the first main surface and also spaced apart from the first plated layer, wherein the chip mounting portion is comprised of a metal material; a first semiconductor chip having a first MOSFET, and including a first surface on which a source electrode is formed; a second semiconductor chip having a second MOSFET, including a second surface on which a drain electrode is formed, and mounted over the first main surface of the chip mounting portion such that the second surface of the second semiconductor chip faces the first plated layer; and a metal plate electrically connecting the source electrode of the first semiconductor chip with the second plated layer, wherein the drain electrode of the second semiconductor chip is electrically connected with the first plated layer via a first conductive material within the first plated layer, wherein the metal plate is electrically connected with the second plated layer via a second conductive material within the second plated layer, and wherein the source electrode of the first semiconductor chip is electrically connected with the drain electrode of the second semiconductor chip, via the metal plate electrically connecting the source electrode with the second plated layer via the second conductive material, the second conductive material within the second plated layer, the second plated layer of the chip mounting portion, the metal material of the chip mounting portion, the first plated layer of the chip mounting portion being electrically connected with the drain electrode via the first conductive material, and the first conductive material within the first plated layer.