| 摘要 |
<p>An input pattern is re-timed in a re-timing circuit (15) by an input clock signal of the same frequency as that of the input pattern, and the re-timed input pattern and a reference pattern generated by a reference pattern generator (21) in synchronization with the input clock signal are compared by a digital error detector (18) to detect a mismatch between them. When the error rate dependent on the thus detected mismatch is larger than a predetermined value, an inhibit control circuit (26) inhibit one input clock pulse which is applied to the reference pattern generator, and when the error rate is smaller than the predetermined value, the inhibit control circuit generates a pattern synchronization establishment signal. When the pattern synchronization establishment signal disappears, a one-shot circuit (32) generates a pulse of a certain width, and if the pattern synchronization establishment signal is not generated again in this while, a T flip-flop (34) is triggered by the trailing edge of the pulse of the certain width. The output of the T flip-flop thus triggered is applied to an inverter (35), which inverts the polarity of the input pulse which is applied to the reference pattern generator and the re-timing circuit. <IMAGE></p> |
