发明名称 PHASE MATCHING CIRCUIT
摘要 <p>PURPOSE:To reduce delay in output data by performing phase matching by changing the temporal position of a time slot which stores the forefront instructing information of input data, and correcting the forefront instructing information corresponding to the change of the temporal position. CONSTITUTION:The input data DIN inputted from a write side is separated to data D1 and the forefront instructing information D2 by a forefront instructing information detection circuit 4. The data D1 of one frame is stored in a temporal memory circuit 2. Meanwhile, the forefront instructing information D2 is inputted to a forefront instructing information correction circuit 5. When a frame pulse G according to the instruction of a readout side is outputted to the temporal memory circuit 2 and the forefront instructing information correction circuit 5, the data D1 is outputted from the temporal memory circuit 2 to a forefront instructing information insertion circuit 6, and also, the forefront instruction information D3 corrected corresponding to the frame pulse G is outputted from the forefront instructing information correction circuit 5 to the forefront instructing information insertion circuit 6, and it is inserted to the data D1, and read out as the output data DOUT to the readout side.</p>
申请公布号 JPH02205131(A) 申请公布日期 1990.08.15
申请号 JP19890025111 申请日期 1989.02.03
申请人 NEC CORP 发明人 KABAYA EIICHI
分类号 H04L7/00 主分类号 H04L7/00
代理机构 代理人
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