CMOS BASED PLANAR TYPE SILICON AVALANCHE PHOTO-DIODE USING SILICON EPITAXIAL LAYER AND FABRICATION METHOD THEREOF
摘要
A CMOS based flat type avalanche photo diode and a manufacturing method thereof are provided to improve a leakage current property of a device and to reduce lattice damage by using a silicon epi layer and an ion implantation using low energy. A well layer(2-2) of a first conductive type is formed inside a substrate(2-1). An avalanche buried layer(2-3) is formed inside the well layer of the first conductive type through a low energy ion implanting process. A silicon epi layer(2-4) is formed in the avalanche buried layer. A p-n junction(2-5a) is formed by forming a doping region of a second conductive type between a partial surface of the well layer of the first conductive type and the avalanche buried layer. A positive electrode(2-7) and a negative electrode(2-8) are formed on the doping region of the second conductive type, and the well layer of the first conductive type of a position separated from the doping region of the second conductive type. An oxide film is formed on a whole surface except for a window in which the positive electrode and the negative electrode are formed.
申请公布号
KR20090061307(A)
申请公布日期
2009.06.16
申请号
KR20070128278
申请日期
2007.12.11
申请人
ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
发明人
YOON, YONG SUN;PARK, KUN SIK;PARK, JONG MOON;KIM, BO WOO;KANG, JIN YEONG