发明名称 Method and apparatus for improving wireability in chip modules
摘要 A method of making a laminated structure includes forming a first lamination having first and second conductive layers having inner and outer surfaces and being spaced apart by a dielectric layer, drilling through the first conductive layer and dielectric layer to form a blind via having a bottom coexistent with the inner surface of the second conductive layer, plating the blind via with a conductive material, and patterning the second conductive layer to form at least one contact pad over the blind via.
申请公布号 AU5005897(A) 申请公布日期 1998.05.29
申请号 AU19970050058 申请日期 1997.10.31
申请人 W.L. GORE + ASSOCIATES INC. 发明人 WILLIAM GEORGE PETEFISH
分类号 H01L23/12;H01L21/48;H01L23/498;H05K1/00;H05K1/05;H05K1/11;H05K3/00;H05K3/42;H05K3/44 主分类号 H01L23/12
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