| 摘要 |
<p>A DLL circuit has a dummy delay (dummy delay circuit 200) corresponding to an internal clock delay relative to an external clock; a variable delay adding circuit including coarse (400) and fine (500) delay circuits for adjusting the delay amount by use of a delay amount adjustment signal; and a phase comparing circuit (300) that compares the phase of the internal clock with that of a delayed clock received via the variable delay circuit and dummy delay to output the delay amount adjustment signal to the variable delay adding circuit. In an initializing mode at the burst commencement, a first signal, which is set to a logic "1" for a period of the internal clock, is inputted to the variable delay adding circuit via the dummy delay, and the duration of the logic "1" of the first signal is determined by the variable delay adding circuit until the end of the period of the internal clock to establish, based on the duration, the delay amount of the coarse delay circuit, thereby performing an initial establishment of the delay amount of the variable delay adding circuit. ® KIPO & WIPO 2007</p> |
