Flash memory codeword architectures

摘要

A flash memory codeword architecture is provided. A non-integer count of logical pages is packed into a codeword payload data container. A codeword payload header is generated. The codeword payload header includes an offset to a first logical page that is packed, at least in part, into the codeword payload data container. The codeword payload data container and the codeword payload header are concatenated to generate a codeword payload. Error-correcting code data is generated based, at least in part, on the codeword payload using a systematic error-correcting code. The codeword payload and error-correcting code data is concatenated to generate a codeword. A physical page is programmed with the codeword.

主权项

1. A method for programming flash memory, the method comprising:
packing, by one or more storage controllers, a non-integer count of logical pages into a first codeword payload data container such that the codeword payload data container contains (i) a first logical page that does not straddle boundaries of the first codeword payload data container and (ii) a first portion of a second logical page, wherein a codeword payload data container size is greater than a size of a single logical page and less than a size of two logical pages; packing, by one or more storage controllers, a second portion of the second logical page into a second codeword payload data container, the second logical page thereby straddling a boundary of the first codeword payload data container and a boundary of the second codeword payload data container; associating, by one or more storage controllers, a first set of three validation bits with the first logical page, wherein the first set of three validation bits describes an arrangement of the first logical page in the first codeword payload data container using a programmed validation bit that indicates that the first logical page is a self-contained logical page; associating, by one or more storage controllers, a second set of three validation bits with the first portion of the second logical page, wherein the second set of three validation bits describes an arrangement of the first portion of the second logical page in the first codeword payload data container using a first pair of consecutive, programmed validation bits, and wherein the first pair of consecutive, programmed validation bits are arranged in the second set of three validation bits such that the second set of three validation bits indicates that the first portion of the second logical page straddles out of the first codeword payload data container; associating, by one or more storage controllers, a third set of three validation bits with the second portion of the second logical page, wherein the third set of three validation bits describes an arrangement of the second portion of the second logical page in the second codeword payload data container using a second pair of consecutive, programmed validation bits, and wherein the second pair of consecutive, programmed validation bits are arranged in the third set of three validation bits such that the third set of three validation bits indicates that the second portion of the second logical page straddles into the second codeword payload data container; generating, by one or more storage controllers, a codeword payload header that includes data describing an offset to the first logical page in the first codeword payload data container; concatenating, by one or more storage controllers, the first codeword payload data container and the codeword payload header to generate a codeword payload; generating, by one or more storage controllers, error-correcting code data based, at least in part, on the codeword payload using a systematic error-correcting code; concatenating, by one or more storage controllers, the codeword payload and error-correcting code data to generate a codeword; and programming, by one or more storage controllers, a physical page with the codeword, wherein the physical page stores a non-zero integer count of codewords.