发明名称 Semiconductor device and scan test method
摘要 A semiconductor device includes a clock signal separating circuit and a logic circuit. The clock signal separating circuit separates a clock signal into a first separation clock signal and a second separation clock signal and to supply the second separation clock signal to a test circuit. The logic circuit generates an output clock signal from the first separation clock signal and a first scan clock signal to the test circuit. A second scan clock signal is supplied to the test circuit.
申请公布号 US2006225010(A1) 申请公布日期 2006.10.05
申请号 US20060391193 申请日期 2006.03.29
申请人 NEC ELECTRONICS CORPORATION 发明人 SERA YOSHIAKI
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
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