发明名称 |
Protection of semiconductor-oxide-containing gate dielectric during replacement gate formation |
摘要 |
Semiconductor-oxide-containing gate dielectrics can be formed on surfaces of semiconductor fins prior to formation of a disposable gate structure. A high dielectric constant (high-k) dielectric spacer can be formed to protect each semiconductor-oxide-containing gate dielectric. Formation of the high-k dielectric spacers may be performed after formation of gate cavities by removal of disposable gate structures, or prior to formation of disposable gate structures. The high-k dielectric spacers can be used as protective layers during an anisotropic etch that vertically extends the gate cavity, and can be removed after vertical extension of the gate cavities. A subset of the semiconductor-oxide-containing gate dielectrics can be removed for formation of high-k gate dielectrics for first type devices, while another subset of the semiconductor-oxide-containing gate dielectrics can be employed as gate dielectrics for second type devices. The vertical extension of the gate cavities increases channel widths in the fin field effect transistors. |
申请公布号 |
US9431395(B2) |
申请公布日期 |
2016.08.30 |
申请号 |
US201414320760 |
申请日期 |
2014.07.01 |
申请人 |
International Business Machines Corporation |
发明人 |
Costrini Gregory;Ramachandran Ravikumar;Vega Reinaldo A.;Wise Richard S. |
分类号 |
H01L29/51;H01L27/088;H01L21/8234;H01L29/06;H01L21/762;H01L21/306;H01L21/308;H01L29/66;H01L21/311 |
主分类号 |
H01L29/51 |
代理机构 |
Scully, Scott, Murphy & Presser, P.C. |
代理人 |
Scully, Scott, Murphy & Presser, P.C. ;Meyers Steven J. |
主权项 |
1. A semiconductor structure comprising:
a semiconductor fin located on a substrate; a shallow trench isolation layer in contact with sidewalls of a lower portion of said semiconductor fin; a semiconductor-oxide-containing gate dielectric in contact with sidewalls of an upper portion of said semiconductor fin; and a gate electrode straddling said semiconductor fin and overlying said semiconductor-oxide-containing gate dielectric, wherein a portion of said gate electrode protrudes downward into a recess within said shallow trench isolation layer, and is laterally spaced from said lower portion of said semiconductor fin by a vertical portion of said shallow trench isolation layer. |
地址 |
Armonk NY US |