DIGITAL PHASE CONTROLLED PLLS

摘要

A digital solution for phase control of an output of a phase-locked loop (PLL) (100) is provided to achieve a desired phase shift at the output of the PLL (100). To that end, a fraction of the pulses of a PLL feedback signal are time shifted to achieve a desired average time shift associated with the desired phase shift. As a result, a desired phase shift is generated at the output of the PLL (100), while a desired devisor of the feedback signal is maintained on average. The resulting digital solution provides highly accurate phase control.