发明名称 CLOCK SUPPLYING DEVICE
摘要 <p>PROBLEM TO BE SOLVED: To quickly discover a deteriorated clock, and to always supply a stable clock to a low order node by changing the destination of clock reception at the time of receiving a clock whose quality is abnormal, and interrupting the input and allowing a network synchronizing oscillator to self-advance when the quality of all the destination of reception is abnormal. SOLUTION: This device is provided with a clock receiving circuit 61, clock selection switching circuit 62, network synchronizing oscillator 63, frequency converting circuit 64, clock distributing circuit 65, and controller 66. The controller 66 is provided with an abnormality detecting circuit which detects abnormality related with a preliminarily set item, and a circuit for allowing the network synchronizing oscillator to self-advance when a clock signal is not received. That is, the circuit for allowing the network synchronizing oscillator to self- advance interrupts an input to a clock supplying device when the time integrated value of the compared results of collected data with mean values is beyond a threshold value for all docks, and allows the network synchronizing oscillator to self-advance by using a reference value before interruption as the control data of the network synchronizing oscillator when the input of the receiving circuit is interrupted.</p>
申请公布号 JPH1132384(A) 申请公布日期 1999.02.02
申请号 JP19970186400 申请日期 1997.07.11
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 FUJIKAWA SHUICHI;YAMAO CHIZURU
分类号 H04L7/00;H04Q11/04;(IPC1-7):H04Q11/04 主分类号 H04L7/00
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