Determining whether a branch instruction is predicted based on a capture range of a second instruction

摘要

An electronic processor is provided for use with a memory (2530) having selectable memory areas. The processor includes a memory area selection circuit (MMU) operable to select one of the selectable memory areas at a time, and an instruction fetch circuit (2520, 2550) operable to fetch a target instruction at an address from the selected one of the selectable memory areas. The processor includes an execution circuit (Pipeline) coupled to execute instructions from the instruction fetch circuit (2520, 2550) and operable to execute a first instruction for changing the selection by the memory area selection circuit (MMU) from a first one of the selectable memory areas to a second one of the selectable memory areas, the execution circuit (Pipeline) further operable to execute a branch instruction that points to a target instruction, access to the target instruction depending on actual change of selection to the second one of the memory areas; and the processor includes a logic circuit (3108, 3120, 3125, 3130, 3140) operable to ensure fetch of the target instruction in response to the branch instruction after actual change of selection. Other circuits, devices, systems, apparatus, and processes are also disclosed.

主权项

1. An electronic processor for use with a memory having selectable memory areas, the processor comprising:
a memory area selection circuit operable to select one of the selectable memory areas at a time; an instruction fetch circuit operable to fetch a target instruction at an address from the selected one of the selectable memory areas; an execution circuit coupled to execute instructions from said instruction fetch circuit and operable to execute a first instruction for changing the selection by said memory area selection circuit from a first one of the selectable memory areas to a second one of the selectable memory areas, said execution circuit further operable to execute a branch instruction which points to an address; a branch predictor circuitry for predicting branch behavior of the branch instruction to predict a target address of the branch instruction, the branch predictor circuitry connected to the instruction fetch circuit to cause the instruction fetch circuit to early fetch an instruction from the predicted target address, the branch predictor circuitry operable to be updated in response to a prior prediction and execution of a branch instruction; and a logic circuit connected to the instruction fetch circuit and the branch predictor circuitry, said logic circuit operable to
detect the first instruction for changing the selection by said memory area selection circuit,detect whether a branch instruction is within a capture range of the detected first instruction, disable said branch prediction circuitry in response to a branch instruction being detected to be within the capture range of the detected first instruction, and suppress update of the branch predictor circuitry in response to a branch instruction being detected to be within the capture range of the detected first instruction.