Dynamically controlling clocking rate of a processor based on user defined rule

摘要

Systems, methods, and other embodiments associated with controlling a clocking rate of a processor clock are described. According to one embodiment, an apparatus includes a register, a selector, and a clock gate. The register stores a set of bits arranged in a clocking pattern. In response to receiving an edge of a first clock signal, the selector selects a bit of the set of bits in the register. With each edge of the first clock signal, the selector selects a next bit in the clocking pattern. The clock gate implements a conjunction of the selected bit and the edge. The clock gate then outputs the conjunction of the selected bit and the edge as a second clock signal.

主权项

1. An apparatus comprising:
a register configured to store a set of bits arranged in a clocking pattern, wherein the clocking pattern is configured to be applied to a first clock signal to generate a second clock signal for clocking a component of the apparatus; a rule enforcement logic configured to enforce at least one user defined rule on the clocking pattern, by:
determining whether the clocking pattern violates the at least one user defined rule including determining whether the clocking pattern produces a clock signal that causes an unpredictable operation of the component being clocked, in view of the user defined rule; andin response to determining that the clocking pattern violates the user defined rule, adjusting the clocking pattern such that the clocking pattern conforms with the at least one user defined rule: a selector configured to select a bit of the set of bits in the register in response to receiving an edge of the first clock signal such that, with each edge of the first clock signal, the selector selects a next bit in the clocking pattern; and a clock gate configured to:
(i) implement a conjunction of the selected bit from the clock pattern and the edge from the first clock signal, and(ii) output the conjunction of the selected bit and the edge as the second clock signal for clocking at least the component; wherein the rule enforcement logic comprises: a shifting history buffer configured to store a predetermined number of previously selected bits from the register, wherein the rule enforcement logic is configured to compare contents of the shifting history buffer to the at least one user defined rule that is stored to determine if the clocking pattern violates the at least one user defined rule.